Electronic Sleep Stage Classifiers: A Survey and VLSI Design Methodology.

Kassiri, Hossein; Chemparathy, Aditi; Salam, M Tariqus; Boyce, Richard; Adamantidis, Antoine Roger; Genov, Roman (2016). Electronic Sleep Stage Classifiers: A Survey and VLSI Design Methodology. IEEE transactions on biomedical circuits and systems, 11(1), pp. 1-12. Institute of Electrical and Electronics Engineers IEEE 10.1109/TBCAS.2016.2540438

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First, existing sleep stage classifier sensors and algorithms are reviewed and compared in terms of classification accuracy, level of automation, implementation complexity, invasiveness, and targeted application. Next, the implementation of a miniature microsystem for low-latency automatic sleep stage classification in rodents is presented. The classification algorithm uses one EMG (electromyogram) and two EEG (electroencephalogram) signals as inputs in order to detect REM (rapid eye movement) sleep, and is optimized for low complexity and low power consumption. It is implemented in an on-board low-power FPGA connected to a multi-channel neural recording IC, to achieve low-latency (order of 1 ms or less) classification. Off-line experimental results using pre-recorded signals from nine mice show REM detection sensitivity and specificity of 81.69% and 93.86%, respectively, with the maximum latency of 39 [Formula: see text]. The device is designed to be used in a non-disruptive closed-loop REM sleep suppression microsystem, for future studies of the effects of REM sleep deprivation on memory consolidation.

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